(A) Field of the Invention
The present invention relates to an integrated circuit utilizing MOS transistor, and more particularly, to a trench-type and planer-structured power MOS transistor.
(B) Description of the Related Art
Power MOS transistors are a specific type of MOS transistor used for providing and switching power in an integrated circuit. Accordingly, power MOS transistors must be able to work normally under high voltage. Therefore, it is typical for a power MOS transistor cell manufactured by CMOS process to be of a large size, usually 5 to 10 times the size of a standard CMOS transistor, in order to be capable of operation under high voltage. On the other hand, it is also a requirement that power MOS transistors be able to output large current. Therefore, it is typical to combine a large number of power MOS transistor cells into a single power MOS transistor, wherein each power MOS transistor cell outputs a relatively small amount of current. However, such a power MOS transistor must be very large, which may be unacceptable in view of manufacturing requirements nowadays.
To reduce the size of power MOS transistors, a vertical diffused MOS (VDMOS) transistor is introduced. FIG. 1 shows a schematic view of a VDMOS transistor. Unlike traditional planar CMOS transistors, the current flows vertically in a VDMOS transistor. As shown in FIG. 1, the source region is on the top of the VDMOS transistor 100, and the drain region is on the bottom of the VDMOS transistor 100. Such structure enables the VDMOS transistor 100 both a high breakdown voltage and a high current output. However, a JFET effect emerges when scaling down VDMOS transistors that increase the resistance of VDMOS transistors.
To solve the JFET effect problem, a trench gate MOS transistor, also referred as a UMOS transistor, is introduced. FIG. 2 shows a schematic view of a UMOS transistor. The name “UMOS” derives from the U-shaped gate oxide of the UMOS transistor 200. As shown in FIG. 2, the UMOS transistor 200 has a trench-shaped gate extending into the silicon. Such structure effectively solves the JFET effect problem. However, since most UMOS transistors comprise an epitaxial layer, when scaling down UMOS transistors, the resistance of the epitaxial layer will increase as well. Therefore, the current increase gained by scaling down UMOS transistors is almost completely offset by the current decrease due to the increased resistance of the epitaxial layer.
On the other hand, since VDMOS and UMOS transistors both adopt a vertical structure, they cannot be manufactured or even integrated with other logic circuits on a CMOS-processed chip. Therefore, there is a need to design a power MOS transistor that can maintain a high breakdown voltage, be of a small size, and can still be implemented on a CMOS processed chip.